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@ -14,6 +14,9 @@
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* currently alpha, uses interrupts, single master/single slave operation
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*/
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uint8_t readbuf[4];
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uint8_t writebuf[4];
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uint8_t pos;
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@ -70,6 +73,7 @@ void spi_init(){
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#ifndef SPI_MASTER
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SPCR |= _BV(SPIE); //enable interrupts
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#endif
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pos = 0;
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}
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@ -116,29 +120,25 @@ void spi_mst_write_read(uint8_t len, uint8_t *data){
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#ifndef SPI_MASTER
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void __attribute__((always_inline)) spi_sla_handle_packet(){
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void spi_sla_handle_packet(){
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// TODO: make slave not hangup in case of partial read
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uint8_t opcode, addr, do_write;
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uint16_t data;
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SPI_WAIT;
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SPDR = 0x53; // random ack
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SPI_WAIT;
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opcode = SPDR;
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opcode = readbuf[0];
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addr = readbuf[1];
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do_write = spi_proto_needswrite(opcode);
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SPI_WAIT;
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addr = SPDR;
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SPDR = 0x00; // buys some pause
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if(do_write){
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data = spi_proto_handlewrite(opcode, addr);
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SPI_WAIT;
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SPDR = data >> 8;
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SPI_WAIT;
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SPDR = data & 0xff;
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writebuf[0]=opcode;
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writebuf[1]=addr;
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writebuf[2]=(data>>8)&0xff;
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writebuf[3]=(data)&0xff;
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} else {
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SPI_WAIT;
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data = SPDR << 8;
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SPI_WAIT;
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data |= SPDR;
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writebuf[0]=0;
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writebuf[1]=0;
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writebuf[2]=0;
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writebuf[3]=0;
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data = (readbuf[3]<<8)&0xff | readbuf[4];
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spi_proto_handleread(opcode, addr, data);
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}
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}
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@ -146,13 +146,16 @@ void __attribute__((always_inline)) spi_sla_handle_packet(){
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ISR(SPI_STC_vect){
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uint8_t a;
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a = SPDR;
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SPDR = ~a;
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/* SPCR &= ~(_BV(SPIE)); //disable spi interrupts
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spi_sla_handle_packet();
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SPCR |= _BV(SPIE);
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*/
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SPDR = *(writebuf+pos);
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*(readbuf+pos) = SPDR;
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pos++;
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if(SPI_SSIN & _BV(SPI_SS_PIN)){
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pos=0;
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SPCR &= ~(_BV(SPIE));
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sei();
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spi_sla_handle_packet();
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SPCR |= _BV(SPIE);
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}
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}
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#endif //not SPI_MASTER
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