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182 lines
3.4 KiB
182 lines
3.4 KiB
#include <avr/io.h>
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#include <stdint.h>
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#include <math.h>
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#include <avr/interrupt.h>
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#include <util/delay.h>
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#include "main.h"
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#include "spi.h"
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/* SPI framework.
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*
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* currently alpha, uses interrupts, single master/single slave operation
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*/
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uint8_t readbuf[5];
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uint8_t writebuf[5];
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uint8_t pos;
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void spi_init(){
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uint8_t spcr, spsr, d;
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/* calculate clock divisor,
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* gcc with optimize will do that calculation compile-time. */
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uint8_t spi_clock_divisor(){
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double d;
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d = F_CPU / SPI_BAUDRATE;
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d = ceil((log(d)/log(2))*0.95); // clock needs dividing by 2^d
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// the 0.95 to avoid ceil issues
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return d-1; // the -1 because minimum divisor is /2
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}
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/* do pseudo-calculation in preprocessor, to get warnings
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* we right-shift 8 times; if result >0, d will be >7
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* so output warning in that case
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*/
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#define D_VAL (F_CPU / SPI_BAUDRATE)
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#if ((D_VAL >> 8) > 0 )
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#warning "spi baudrate too slow, cannot be set (clamped to minimum)"
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#endif
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d = spi_clock_divisor();
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if(d>7){
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// warning was (hopefully) output previously by cpp
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d=7;
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}
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//DDRs setzen
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#ifdef SPI_MASTER
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DDRB |= _BV(5) | _BV(3) | _BV(2); //MOSI, SCK, unused SS
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DDRB &= ~( _BV(4)); //MISO
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SPI_SSDDR |= _BV(SPI_SS_PIN); // actually used SS
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#else //SPI_MASTER
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DDRB |= _BV(4); //MISO
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DDRB &= ~( _BV(5) | _BV(3) | _BV(2)); //MOSI, SCK, SS
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#endif //SPI_MASTER
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spsr = 0;
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spsr |= (d & 1) ? 0 : _BV(SPI2X);
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spcr = 0 | _BV(SPE);
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spcr |= (d & 2) ? _BV(SPR0) : 0;
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spcr |= (d & 4) ? _BV(SPR1) : 0;
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#ifdef SPI_MASTER
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spcr |= _BV(MSTR);
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#endif
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SPSR = spsr;
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SPCR = spcr;
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#ifndef SPI_MASTER
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SPCR |= _BV(SPIE); //enable interrupts
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PCMSK0 |= _BV(2);
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PCICR |= _BV(0);
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#endif
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pos = 0;
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}
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void spi_mst_start_packet(){
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#ifdef SPI_MASTER
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_delay_us(2*1e6/SPI_BAUDRATE);
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SPI_SSOUT &= ~(_BV(SPI_SS_PIN));
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_delay_us(2*1e6/SPI_BAUDRATE);
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#endif
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}
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void spi_mst_end_packet(){
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#ifdef SPI_MASTER
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_delay_us(2*1e6/SPI_BAUDRATE);
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SPI_SSOUT |= _BV(SPI_SS_PIN);
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_delay_us(2*1e6/SPI_BAUDRATE);
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#endif
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}
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#define SPI_WAIT while(!(SPSR & _BV(SPIF))){;}
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void spi_mst_write(uint8_t len, uint8_t *data){
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while(len>0){
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SPDR = *data++;
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len--;
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SPI_WAIT;
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}
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}
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void spi_mst_read(uint8_t len, uint8_t *data){
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while(len>0){
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SPDR = 0;
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len--;
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SPI_WAIT;
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*data++ = SPDR;
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}
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}
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void spi_mst_write_read(uint8_t len, uint8_t *data){
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while(len>0){
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SPDR = *data;
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len--;
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SPI_WAIT;
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*data++ = SPDR;
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}
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}
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void spi_mst_packet_delay(){
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// wait for 2 byte
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_delay_us(16*1e6/SPI_BAUDRATE);
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}
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#ifndef SPI_MASTER
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void spi_sla_handle_packet(){
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// TODO: make slave not hangup in case of partial read
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uint8_t opcode, addr;
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uint16_t data, newdata;
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writebuf[0] = 0; // generate invalid replies, so no inconsistent packets
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// are sent.
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opcode = readbuf[0];
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addr = readbuf[1];
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data = (readbuf[2]<<8) | readbuf[3];
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newdata = spi_proto_slaveaction(opcode, addr, data);
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writebuf[1]=addr;
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writebuf[2]=(newdata>>8)&0xff;
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writebuf[3]=(newdata)&0xff;
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writebuf[0]=opcode; // set opcode last to validate packet (it's a kind of locking)
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}
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ISR(SPI_STC_vect){
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SPDR = writebuf[pos];
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readbuf[pos] = SPDR;
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pos++;
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if(pos>=5){
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pos=4;
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}
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}
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ISR(PCINT0_vect){ // SS-line changed
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if(SPI_SSIN & _BV(SPI_SS_PIN)){ // SS-line was actually released
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pos=0;
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SPCR &= ~(_BV(SPIE));
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sei();
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spi_sla_handle_packet();
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SPCR |= _BV(SPIE);
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}
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}
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#endif //not SPI_MASTER
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